Image-display devices, typified by liquid crystal displays, etc., performs high-speed image display by sequentially reading the data of one frame of an image into a temporary storage device referred to as a frame buffer, reading out the data in parallel at predetermined intervals, and then inputting the read out data to each pixel of an image-display device. The frame buffer is arranged in an array in the vicinity of an image-display panel of an image-display device, and comprises a circuit element referred to as a shift register. Such a shift register comprises two or more latch circuits and flip-flop circuits.
Hereinafter, these elements are described with reference to FIGS. 1 to 3. The image-display panel and frame buffer incorporated into an image-display device are described with reference to FIG. 1.
FIG. 1 illustrates an image-display panel 101, an X-axis (longitudinal) frame buffer 105, and a Y-axis frame buffer 106, with the image-display panel 101 comprising n×m pixels 102, n rows deep and m columns wide. Display or non-display of each pixel is determined by the overlapping of signals input from two signal lines; a signal line 103 in the longitudinal direction and a signal line 104 in the transverse direction. Signals are input to the signal lines; the signal line 103 in the longitudinal direction and the signal line 104 in the transverse direction, via the X-axis frame buffer 105 and the Y-axis frame buffer 106, respectively.
The X-axis frame buffer and the Y-axis frame buffer are configured in almost the same manner. The configuration is described in the following taking the X-axis frame buffer 105 as an example. The X-axis frame buffer 105 comprises at least one shift register 107 to which signals D are sequentially input by a signal input line 108 and to which at least one so-called clock signal is input so as to synchronize a circuit operation. In this case, two clock signals of CK1 and CK2 are input by clock signal lines 109 and 110.
The signals D sequentially input to the shift register 107 are transmitted to successive flip-flops in the shift register for each clock cycle in accordance with the clock signals, and thus the signals are input to the desired number of flip-flops. In accordance with the clock signal CK3 for outputting an image input via the clock signal line 111, the signals D are output in parallel to the image-display panel 101 from a signal output line 112.
The content of the shift register 107 is described with reference to FIGS. 2(a) and (b). FIG. 2(a) illustrates a shift register 201, the shift resister 201 being one of the shift registers 107 in the frame buffer 105 in FIG. 1, while FIG. 2(b) illustrates the details.
As shown in FIG. 2(b), the shift register herein is provided with a latch. More specifically, the shift register comprises a shift-register portion 202 and a latch portion 203.
The shift-register portion 202 includes two or more flip-flops 204, and the respective flip-flops 204 are connected to each other by a signal line 205 to which a signal D is input, and a clock line 206 to which a clock signal is input. The latch portion 203 also includes two or more flip-flops 204, and the individual flip-flops 204 in the latch portion 203 are connected to the individual flip-flops 204 in the shift-register portion 202 by the signal line 207 to which a signal D is input. A clock line 208 is connected to the individual flip-flops 204 in the latch portion 203, and a second clock signal CK2 is input thereto by the clock line 208.
An output signal line 209 extends from the individual flip-flops 204 in the latch portion 203. A gate 210 is connected to each output signal line 209, and an output signal is input to the image panel in accordance with the clock signal input from the clock line 206. The signals input sequentially are transmitted to the individual flip-flops in the shift register for each clock cycle of the clock signals, and the signals are then transmitted to the desired number of flip-flops. Values input to the individual flip-flops for each clock timing are held at a latch portion. The data held at the latch portion 203 are output in parallel at the desired timing in accordance with the clock signal CK3 supplied to a gate 210, thereby displaying an image on the image panel.
The content of the flip-flop in the shift register is described with reference to FIGS. 3(a) and (b). Details of this flip-flop are given in, for example, “How to use a flip-flop”, Transistor GIJUTSU (transistor technology) SPECIAL, CQ Publishing Co., Ltd., No. 58, pp. 114–127.
FIG. 3(a) illustrates details of the flip-flop 204 of FIG. 2(b). As shown in FIG. 3(a), the flip-flop comprises an inverter and a clocked inverter. The input signal D is input to an inverter 301 via a first clocked inverter 302, and subsequently the output of the inverter 301 is fed back to the input of the inverter 301 through a second clocked inverter 303. In other words, the portion surrounded by a dotted line 304 serves as a first feedback circuit.
The output of the first feedback circuit 304 is input to a second inverter 306 via a third clocked inverter 305. Subsequently, the output of the second inverter 306 is fed back to the input of the second inverter 306 via a fourth clocked inverter 307. In other words, the portion surrounded by a dotted line 308 serves as a second feedback circuit.
The output of the second inverter 306 is output as the output Q of this flip-flop, and a signal fed back to the input of the second inverter 306 is output as −Q which is inverted to the output Q, (designated “Q bar”, which may be represented as “{overscore (Q)}”). The first feedback circuit 304 is referred to as a master latch, and the second feedback circuit 308 is referred to as a slave latch. A flip-flop circuit thus configured is referred to as a master-slave flip-flop circuit.
A clock signal is input to each clocked inverter from a clock circuit 309. Under the state shown in FIG. 3(a), an inverted clock signal −CK, which is inverted to the clock signal CK, is input to the first and fourth clocked inverters (302, 307), and a clock signal CK is input to the second and third clocked inverters (303, 305). Thus, the master latch and the slave latch are configured such that a signal is transmitted from the master latch to the slave latch for each clock cycle, which avoids signal transmission to both the master latch and the slave latch within one clock cycle.
The clock circuit 309 is not always incorporated into a flip-flop circuit, and it may be provided externally. In general, a clocked inverter is configured as shown in FIG. 3(b). The phase of a clock signal supplied to an n-channel MOSFET in which the source is grounded is opposite to that of a clock signal supplied to a p-channel MOSFET in which the source is connected to the power supply.
Prior-art flip-flop circuits configured as above are difficult to reduce the power consumption thereof because there is the necessity of continuously supplying power for storing the input data so as to avoid data loss caused by power supply interruption.
In the case of power supply interruption, data preceding power supply interruption need to be input again to a flip-flop circuit for outputting, resulting in a loss in processes. Also, since prior-art flip-flop circuits need to supply power throughout the circuit to read out data stored in the flip-flop circuit, there is room for improvement in terms of reducing the power consumption in this point.